1. Field of the Invention
The present invention relates to a driving apparatus for controlling the switching operation of a pair of field effect transistors (hereinafter FETs) connected in series between two different potentials to function as switching devices. The present invention relates also to a DC/DC converter employing such a driving apparatus.
2. Description of the Prior Art
A synchronous-rectification DC/DC converter has a pair of FETs connected in series between two different potentials (between an input potential and a ground potential) to function as switching devices for achieving synchronous rectification, and a desired voltage is output from the node between the two FETs through an LC filter. Such a synchronous-rectification DC/DC converter incorporates an FET driving apparatus for controlling the switching operation of the FETs, and this driving apparatus is provided with a function for preventing the two FETs from being turned on simultaneously. This is because, if a flow-through current flows through the two FETs, it may destroy them, or lower conversion efficiency.
One way to prevent the two FETs from being turned on simultaneously is to secure a period in which both FETs are simultaneously off by delaying the timing with which one FET is turned from off to on relative to the timing with which the other FET is turned from on to off so that the two FETs are not switched on or off until the end of that “simultaneously-off” period. To achieve this, a conventional FET driving apparatus adopts one of the techniques of (1) forming a delay circuit including a CR time constant circuit and a plurality of inverters, (2) varying the slice level of a triangular wave used to produce the gate voltages, (3) controlling one gate voltage according to the result of monitoring the other gate voltage, and (4) controlling the gate voltages according to the result of monitoring the coil terminal voltage and the gate voltage of the low-side FET (U.S. Pat. No. 5,757,173). All these techniques help secure a period in which both FETs are simultaneously off.
It is true that, to a certain extent, an FET driving apparatus configured as described above serves to prevent the two FETs from being turned on simultaneously.
However, in an FET driving apparatus adopting the technique (1) or (2) above, a predetermined length of time is previously secured as the simultaneously-off period without monitoring whether the FETs are on or off. Thus, to securely prevent the two FETs from being turned on simultaneously, quite inconveniently, it is necessary to optimize the length of the simultaneously-off period for the particular FETs actually driven. In particular, in a case where the FETs actually driven are externally fitted ones (as in a large-current DC/DC converter), variations in their characteristics and type are completely independent of variations in those of the IC built in the FET driving apparatus. This makes it inevitable to add an ample margin to the simultaneously-off period, leading to lower conversion efficiency.
In an FET driving apparatus adopting the technique (3) or (4) above, whether the FETs are on or off is detected according to their gate voltages. Thus, no consideration is given to the turn-on/off delay of the FETs (i.e., the delay that occurs after the gate voltages are varied until a change appears in the output voltage). As a result, despite the monitoring of the gate voltages, quite inconveniently, it is all the same necessary to optimize the length of the simultaneously-off period for the particular FETs actually driven. The aforementioned turn-on/off delay varies greatly from one FET to another, and is therefore given, in general, not as an actual value but only as a typical value (maximum value) in the specifications of FETs. Accordingly, even when the length of the simultaneously-off period is determined on the basis of what is stated in the specifications of a given type of FET, in reality, unduly low conversion efficiency may result. For example, in a case where the actual value is 30 [nm] while the typical value is 200 [ns], the two FETs are unnecessarily kept simultaneously off for as long as 170 [ns].
Furthermore, an FET driving apparatus adopting the technique (4) above functions properly only in a case where, when both FETs are simultaneously off, a current flows through the coil in a positive direction (i.e., from ground to the output terminal). That is, quite inconveniently, such an FET driving apparatus does not function properly in a case where, when both FETs are simultaneously off, a current flows through the coil in a negative direction (i.e., from the output terminal to ground). This is because, in that case, the body diode attached to the high-side FET is on, and thus causes the coil terminal voltage to remain close to the input voltage. This type of FET driving apparatus is thus unusable in a DC/DC converter for supplying electric power to a load that requires the direction of the coil current to be switched during operation (such as a variable-supply-voltage IC or DDR-SDRAM (double-data-rate synchronous dynamic random-access memory)).